Last week IBM announced their next generation mainframe CPU Telum. Manufactured by Samsung’s 7nm node, each Telum processor has 8 cores with each core running at a base 5GHz. Two processors are combined in a package similar to AMD’s chiplet design. A drawer in each mainframe can hold 4 packages (sockets), and the mainframe can hold 4 drawers for combined 256 cores.
Different from previous generations, there is no dedicated L3 or L4 cache. Instead each core has a 32MB L2 cache that can pool to become a 256MB L3 “virtual” cache on the same processor or 2GB L4 “virtual” cache on the same drawer. Also included to help with AI is a on-die but not on-core inference accelerator running at 6TFLOPS using Intel’s AVX-512 to communicate with the cores.
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